l Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane systems
l Compatible with I2C standard mode, I2C fast mode and SMBus standards
l Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6V threshold) with ability to disable ΔV/Δt rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same
l 5V to 3.3V level translation with optimum noise margin
l High-impedance SDAn and SCLn pins for VCC or VCC2 = 0V
l 1V precharge on all SDAn and SCLn pins
l Supports clock stretching and multiple master arbitration and synchronization
l Operating power supply voltage range: 2.7V to 5.5V
l 0Hz to 400kHz clock frequency
