l Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
l Compatible with I2C standard mode, I2C fast mode and SMBus standards
l Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6V threshold) requires the bus pull-up voltage and supply voltage (VCC) to be the same
l Active HIGH EN input
l Active HIGH READY open-drain output
l 1V precharge on all SDA and SCL lines
l Supporting clock stretching and multiple master arbitration/synchronization
l Operating power supply voltage range: 2.7V to 5.5V
l 0Hz to 400kHz clock frequency
